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dual-phase single or two output synchronous step-down controller sc2443 power management aug. 2008 1 typical application circuit features u wide input voltage range: 4.7v to 16v u 0.5v feedback voltage for low-voltage outputs u programmable frequency up to 1 mhz per phase u 2-phase synchronous continuous conduction mode for high efciency step-down converters u out-of-phase operation for low input current ripples u output source and sink currents u fixed frequency peak current-mode control u 75mv/-110mv maximum current sense voltage u inductor dcr current-sensing for low-cost applications u dual outputs or 2-phase single output operation u excellent current sharing between individual phases u individual soft-start, overload shutdown and enable u external reference input for ddr applications u external synchronization u industrial temperature range u 4mm x 4mm x1mm 24-lead mlpq package description t he sc2443 is a high-frequency dual synchronous step-down switching power supply controller. it provides out-of-phase high-current output gate drives to all n-channel mosfet power stages. the sc2443 operates in synchronous continuous-con - duction mode. both phases are capable of maintaining regula - tion with sourcing or sinking load currents, making the sc2443 suitable for generating both vddq and the tracking vtt for ddr applications. the sc2443 employs fxed frequency peak current-mode con - trol for the ease of frequency compensation and fast transient response. the dual-phase step-down controllers of the sc2443 can be used to produce two individually controlled and regulated out - puts or a single output with shared current in each phase. the step-down controllers operate from an input of at least 4.7v and are capable of regulating outputs as low as 0.5v individual soft-start and overload shutdown timer is included in each step-down controller. the sc2443 implements hiccup overload protection. in single output current share confgura - tion, the master timer controls the soft-start and overload shut - down functions of both controllers. applications u telecommunic ation power supplies u ddr memory power supplies u graphic power supplies u servers and base stations vout1 in2- vp1 vin vin vout1 in2- vp1 vin in1- u1 sc2443 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 in1- comp1 sync agnd ref refin comp2 in2- cs2- cs2+ ss2/en2 avcc bst2 gdh2 gdl2 pgnd pvcc gdl1 gdh1 bst1 ss1/en1 cs1+ cs1- rosc in1- vout2 vin vp1 in1- vp1 vin vin vin u1 sc2443 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 in1- comp1 sync agnd ref refin comp2 in2- cs2- cs2+ ss2/en2 avcc bst2 gdh2 gdl2 pgnd pvcc gdl1 gdh1 bst1 ss1/en1 cs1+ cs1- rosc vout1 vin in1- vout1 dual independent outputs single output with current sharing
sc2443 2 pin confguration ordering information marking information notes: ( ) available in tape and reel only. a reel contains 3,000 devices. (2) available in lead-free package only. device is weee and rohs compliant. (24-lead 4mm x 4mm x mm mlpq ) ja = 29 c /w device package sc2443mltrt (1,2) 24-lead 4mm x 4mm x mm mlpq sc2443evb evaluation board top view 1 6 7 12 13 18 24 19 in1- comp1 sync ref agnd ref in comp2 in2- cs2- cs2+ avcc ss2/en2 gdl1 pvcc pgnd gdh2 gdl2 bst2 rosc cs1- cs1+ ss1/en1 gdh1 bst1 marking for the 4 x 4mm mlpq-24 package:
sc2443 3 recommended operating conditions absolute maximum ratings exceeding the above specifcations may result in permanent damage to the device or device malfunction. operation outside of the parameters specifed in the electrical characteristics section is not recommended. notes- (1) calculated from package in still air, mounted to 3 x 4.5, 4 layer fr4 pcb with thermal vias under the exposed pad per jesd51 standards. (2) this device is esd sensitive. use of standard esd handing precautions is required electrical characteristics thermal information avcc, pvcc voltage -0.3 to 20v v bst1 , v bst2 voltage -0.3 to 32v - 0.3 to 40v (for <10ns @ freq. < 500khz) ss1/en1, ss2/en2, sync voltage -0.3 to 6v in1-, in2-, ref voltage -0.3 to avcc+ 0.3v ref in , comp1, comp2 voltage -0.3 to avcc+ 0.3v cs1+, cs1-, cs2+, cs2- voltage -0.3 to avcc+ 0.3v pgnd to agnd 0.3v peak ir refow temperature 260c input voltage range 4.75v to 16v junction to ambient (1) 29c/w maximum junction temperature 150c storage temperature -65 to +150c unless otherwise specifed: avcc = pvcc = 12v, v bst1 = v bst2 = 12v, sync = 0v, -40c < t a = t j < 85c, r osc =51.1k w. parameter symbol conditions min typ max units undervoltage lockout avcc start threshold avcc th avcc rising 4.5 4.7 v avcc start hysteresis avcc hyst 170 mv avcc operating current i cc 12 16 ma avcc quiescent current in uvlo i q avcc = avcc th - 0.2v 1.7 ma channel 1 error amplifer non-inverting input voltage v in1+ 0.49 0.5 0.51 v non-inverting input voltage v in1+ 0c < t a = t j < 70c 0.4925 0.5 0.5075 v non-inverting input line regulation avcc th < avcc < 15v 0.02 %/v input ofset voltage 1 mv inverting input bias current i in1- -0.1 -0.25 a amplifer transconductance g m1 260 w -1 amplifer open loop gain a ol1 65 db amplifer unity gain bandwidth 5 mhz comp1 switching threshold v cs1+ =v cs1- = 0, v ss1 rising 2.2 v amplifer output sink current v in1- = 1v, v comp1 = 2.5v 16 a amplifer output source current v in1- = 0v, v comp1 = 2.5v 12 a
sc2443 4 electrical characteristics (continued) parameter symbol conditions min typ max units channel 2 error amplifer input common-mode range () 0 3 v inverting input voltage range () 0 avcc v input ofset voltage .5 mv non-inverting input bias current i in2+ -50 -380 na inverting input bias current i in2- -00 -250 na inverting input voltage for 2 phases single output operation 2.5 v amplifer transconductance g m2 260 w -1 amplifer open loop gain a ol2 65 db amplifer unity gain bandwidth 5 mhz comp2 switching threshold v cs2+ =v cs2- = 0, v ss2 rising 2.2 v amplifer output sink current v comp2 = 2.5v 6 a amplifer output source current v comp2 = 2.5v 2 a oscillator channel frequency f ch , f ch2 450 500 550 khz synchronizing frequency () 2.f ch khz sync input high voltage .5 v sync input low voltage 0.5 v channel maximum duty cycle d max , d max2 88 % channel minimum duty cycle d min , d min2 0 % current limit comparator input common mode range 0 avcc- v cycle by cycle peak currentr limit v ilim+ , v ilim2+ v cs- = v cs2- = 0.5v, sourcing 60 75 90 mv valley current overload shutdown threshold v ilim- , v ilim2- v cs- = v cs2- = 0.5v, sinking -85 -0 -30 mv positive current sense input bias current i cs+ , i cs2+ v cs+ = v cs- = 0 v cs2+ = v cs2- = 0 -0.7 -2 a negative current sense input bias current i cs- , i cs2- v cs+ = v cs- = 0 v cs2+ = v cs2- = 0 -0.7 -2 a
sc2443 5 notes: ( ) guaranteed by design. parameter symbol conditions min typ max units gate drivers high side gate driver peak source current v bst , v bst2 = 2v .5 a high side gate driver peak sink current v bst , v bst2 = 2v a low side gate driver peak source current avcc = pvcc = 2v .5 a low side gate driver peak sink current avcc = pvcc = 2v a gate drive rise time c l = 2200pf 20 ns gate drive fall time c l = 2200pf 20 ns low side gate driver to high side gate driver non-overlapping delay c l = 0 90 ns high side gate driver to low side gate driver non-overlapping delay c l = 0 90 ns minimum on time t a = 25 c 50 ns soft start, overload latchof and enable soft start charging current i ss , i ss2 v ss = v ss2 = .5v 2 a overload enabling soft start voltage v ss and v ss2 rising 3.2 v overload in - threshold v ss = 3.8v, v in- falling 0.75v ref v overload in2- threshold v ss2 = 3.8v, v in2- falling 0.72 x v soft start discharge current i ss _dis , i ss2_dis v ss = v ss2 = 3.8v .4 a overload recovery soft start voltage v ssrcv , v ssrcv2 v ss and v ss2 falling 0.3 0.5 0.7 v gate driver disable ss/en voltage 0.7 0.9 v gate driver enable ss/en voltage .2 .5 v internal 0.5v reference bufer output voltage v ref i ref = -ma 490 500 50 mv load regulation 0 < i ref <-5ma 0.05 %/ma electrical characteristics (continued)
sc2443 6 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 -40 25 85 496 498 500 502 504 506 508 510 512 -40 25 85 2.05 2.10 2.15 2.20 2.25 2.30 2.35 -40 25 85 499.0 499.5 500.0 500.5 501.0 501.5 502.0 -40 25 85 typical characteristics 4.49 4.50 4.51 4.52 4.53 4.54 4.55 -40 25 85 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 -40 25 85 1.55 1.60 1.65 1.70 1.75 1.80 1.85 -40 25 85 avcc uvlo(v) uvlo threshold vs. temperature temperature ( o c) avcc operation current vs. temperature temperature ( o c) avcc operation current(ma) avcc current in uvlo vs. temperature avcc current in uvlo(ma) vref(mv) vref vs. temperature temperature ( o c) comp sink/source current vs. temperature temperature ( o c) comp sink/source current(ua) e/a gm vs. temperature e/a gm(u : - ) comp switching threshold(v) comp switching threshold vs. temperature temperature ( o c) switching frequency setting vs. temperature temperature ( o c) switching frequency(khz) cycle by cycle ocp threshold vs. temperature cycle by cycle ocp threshols(mv) ss/en threshold voltage(v) ss/en threshold for overload hiccup vs. temperature temperature ( o c) ss/en threshold for gate driver enable / disable vs. temperature temperature ( o c) ss/en threshold voltage(v) ss/en threshold voltage(v) temperature ( o c) temperature ( o c) temperature ( o c) temperature ( o c) -15 -10 -5 0 5 10 15 20 -40 25 85 sink source 220 230 240 250 260 270 280 290 -40 25 85 rosc = 5 .k : 71.0 71.5 72.0 72.5 73.0 73.5 74.0 74.5 75.0 -40 25 85 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 -40 25 85 enable disable 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 -40 25 85 ss/en threshold for overload hiccup recovery vs. temperature
sc2443 7 30 40 50 60 70 80 90 1 5 10 15 20 25 30 35 40 typical application circuit performance circuit conditions : single output current share confguration as shown in page 5 soft start 0ms/div vin 2v/div vout v/div comp v/div en/ss 2v/div releasing ss/en pin from gnd vout v/div comp v/div en/ss 2v/div vin 5v/div vout v/div gdl 5v/div en/ss 2v/div vin 5v/div shuting down _ vin ramp down ms/div vin 2v/div vout v/div gdl 0v/div en/ss 2v/div pulling ss/en pin to gnd gate wavefroms gdh2 gdl2 0v/div gdh gdl 0v/div output ripple _ iout = 40a us/div vout 20mv/div transient response _ 0a ~ 30a ocp trip _ iout = 56a vout 50mv/div vout 0.5v/div gdl 0v/div gdh 20v/div ss/en 2v/div 0ms/div 0ms/div vin 5v/div vout v/div gdl 0v/div en/ss 2v/div 400us/div us/div gdh gdh2 0v/div 200us/div 400us/div efciency ( 2vin to vout) iout(a) eff (%) ocp recovery to 30a loading vout 0.5v/div gdl 0v/div gdh 20v/div ss/en 2v/div 20ms/div releasing ss/en pin from gnd
sc2443 8 70 75 80 85 90 95 1 5 10 15 20 typical application circuit performance circuit conditions : dual independent outputs confguration as shown in page 7 soft start (vout ) 0ms/div vin 2v/div vout v/div comp en/ss 2v/div soft start (both outputs) vout2 2v/div comp2 v/div en2/ss2 2v/div vin 2v/div vout2 2v/div ss2/en2 2v/div vout 0.5v/div ss/en 2v/div gate waveforms (vout _2 = 20a) us/div gdh gdl 0v/div gdh2 gdl2 0v/div output ripple (vout _20a) output ripple (vout2_20a) gdh2 gdl2 0v/div transient response (vout _ 2a ~ 7a) 200us/div vout 50mv/div ocp trip (vout = 30a) vout2 50mv/div vout 0.5v/div gdh gdl 20v/div ss/en 2v/div 0ms/div 20ms/div vout 50mv/div gdh gdl 0v/div us/div us/div 200us/div 400us/div combined efciency ( 2vin to vout & 2.5vout) iout(a) eff (%) vout2 v/div gdl2 0v/div gdh2 20v/div ss2/en2 2v/div 400us/div soft start (vout2) vout2 50mv/div transient response (vout2 _ 2a ~ 7a) ocp trip (vout2 = 28a)
sc2443 9 pin descriptions pin # pin name pin function in- inverting input of the error amplifer for the step-down controller . 2 comp the error amplifer output for step-down controller . 3 sync edge-triggered synchronization input. when not synchronized, tie this pin to a voltage above .5v or the ground. an external clock (frequency > frequency set with rosc) at this pin synchronizes the controllers. 4 agnd analog signal ground 5 ref bufered output of the internal 0.5v reference. the non-inverting input of the error amplifer for the step-down converter is internally connected to this pin 6 refin an external reference voltage is applied to this pin.the non-inverting input of the error amplifer for the step-down converter 2 is internally connected to this pin. 7 comp2 the error amplifer output for step-down controller 2. 8 in2- inverting input of the error amplifer for the step-down controller 2. tie to avcc for two-phase single output applications. 9 cs2- the inverting input of the current-sense amplifer/comparator for the controller 2. 0 cs2+ the non-inverting input of the current-sense amplifer/comparator for the controller 2. ss2/en2 an external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch of time for step-down converter 2. pulling this pin below 0.7v shuts of the gate drivers for the second controller. leave open for two-phase single output applications. 2 avcc power supply voltage for the analog portion of the controllers. 3 bst2 bootstrapped supply for the high-side gate drive 2. 4 gdh2 gate drive output for the high-side n-channel mosfet of output 2. 5 gdl2 gate drive output for the low-side n-channel mosfet of output 2. 6 pgnd ground supply for all the gate drivers. 7 pvcc power supply voltage for low-side mosfet drivers. 8 gdl gate drive output for the low-side n-channel mosfet of output . 9 gdh gate drive output for the high-side n-channel mosfet of output . 20 bst bootstrapped supply for the high-side gate drive . 2 ss/en an external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch of time for buck converter . pulling this pin below 0.7v shuts of the gate drivers for the frst controller. 22 cs+ the non-inverting input of the current-sense amplifer/comparator for the controller . 23 cs- the inverting input of the current-sense amplifer/comparator for the controller 24 rosc an external resistor connected from this pin to gnd sets the oscillator frequency thpad solder to the analog ground plane of the pcb.
sc2443 0 sync oscillator ea1 slope comp + 110mv ilim+ clk2 r q s ol soft-start and overload hiccup control uvlo 4.3/4.5v non-overlapping conduction control pwm rosc in1- ref/in1+ cs1+ cs1- clk1 - - + reference 0.5v + ilim- isen + - 75mv ocn comp2 in2- ref in /in2+ agnd ea2 6 dsbl avcc bst1 gdh1 pvcc gdl1 ss1/en1 comp1 + - - + pgnd 4 17 19 20 16 6 8 21 12 18 23 5 1 2 24 3 22 7 + - uvlo - - + + + 0.72 vref out 0.75 vref block diagram figure 1. sc2443 block diagram sc2443 block diagram (channel pwm control only)
sc2443 applications information description the sc2443 is a constant frequency 2-phase current-mode step-down pwm switching controller driving all n-channel mosfet. the two channels of the controller operate at 80 degrees out-of-phase from each other. since input currents are interleaved in a two-phase converter, input ripple current is lower and smaller input capacitor can be used for fltering. also, with lower inductor current and smaller inductor ripple current per phase, overall i 2 r losses are reduced. the sc2443 operates in synchronous continuous- conduction mode. it can be confgured either as two independent step-down controllers producing two separate outputs or as a dual-phase single-output controller by tying the in2- pin to vcc. in single output operation, the channel one error amplifer controls both channels and the channel two error amplifer is disabled. soft-start and overload hiccup of both channels is synchronized to channel one. frequency setting and synchronization the internal oscillator of the sc2443 runs at twice the phase frequency. the free-running frequency of the oscillator can be programmed with an external resistor from the rosc pin to ground. the step-down controllers are capable of operating up to mhz. it is necessary to consider the operating duty-ratio before deciding the switching frequency. see applications information section for more details. when synchronized externally, the applied clock frequency should be twice the desired phase frequency. the synchronizing clock frequency should also be between 2 - 2.6 times the set free-running channel frequency. control loop the sc2443 uses peak current-mode control for fast transient response, ease of compensation and current sharing in single output operation. the low-side mosfet of each channel is turned of at the falling-edge of the phase timing clock. after a brief non-overlapping time interval of 90ns, the high-side mosfet is turned on. the phase inductor current ramps up. when the sensed inductor current reaches the threshold determined by the error amplifer output and compensation ramp, the high-side mosfet is turned of. after a non-overlapping conduction time of 90ns, the low-side mosfet is turned on. the supply voltages for the high-side gate drivers are obtained from two diode-capacitor bootstrap circuits. if the bootstrap capacitor is charged from vcc, the high- side gate drive voltage swing will be from approximately 2vcc to the ground. the power dissipated in the high- side gate driver is not higher with higher voltage swing because the gate-source voltage of the high-side mosfet still swing from zero to vcc. the outputs of the low-side gate drivers swing from vcc to ground. the sc2443 has internal ramp-compensation to prevent sub-harmonic oscillation when operating above 50% duty cycle. there is enough ramp internally for a sensed voltage ripple between /4 to /3 of the full-scale sensed voltage limit of 75mv. the maximum sensed voltage limit is unafected by the compensating ramp. current-sensing there are two ways to sense the inductor current for current-mode control with the sc2443. since the peak inductor current corresponds to 75mv of sensed voltage (cs+ - cs-), resistor current sensing can be used at the output without resulting in excessive power dissipation. although accurate and far easier to lay out than high-side resistor sensing, a pair of precision sense resistors adds cost to the converter. with proper rc flter, inductor dcr sensing can also be used for sc2443 resulting in low cost and without extra power dissipation. error amplifers in closed loop operation, the error amplifer output ranges from . v to 3.5v. the upper output operating range of either error amplifer is reserved for positive current- sense voltage (cs+ - cs-) and corresponds to positive (sourcing) output current. if the amplifer swings to its lower operating range, the amplifer will still modulate the high-side gate drive duty-ratio. however the peak current- sense voltage (hence the peak inductor current) will be limited to a negative value. the error amplifer output is about 2.2v when the peak sense-voltage is zero. the built-in ofset in the current sense amplifer together with synchronous continuous-conduction mode of operation allows the sc2443 to regulate the output irrespective of the direction of the load current.
sc2443 2 current reaching its current limit and the instant the converter shuts down. this is due to cycle skipping(a consequence of inductor current sense) reduces the actual operating frequency. the ss/en pin can also be used as the enable input for that channel. both the high-side and the low-side mosfets will be turned of if the ss/en pin is pulled below 0.7v. operating frequency (fs) the switching frequency in the sc2443 is user- programmable. the advantages of using constant frequency operation are simple passive component selection and ease of feedback compensation. before setting the operating frequency, the following trade-ofs should be considered. ) passive component size 2) circuitry efciency 3) emi condition 4) minimum switch on time and 5) maximum duty ratio for a given output power, the sizes of the passive components are inversely proportional to the switching frequency, whereas mosfet and diodes switching losses are proportional to the operating frequency. other issues such as heat dissipation, packaging and the cost issues are also to be considered. the frequency bands for signal transmission should be avoided because of em interference. minimum switch on time consideration in the sc2443 the falling edge of the clock turns on the top mosfet. the inductor current and the sensed voltage ramp up. after the sensed voltage crosses a threshold determined by the error amplifer output, the top mosfet is turned of. the propagation delay time from the turn- on of the controlling fet to its turn-of is the minimum switch on time. the sc2443 has a minimum on time of about 50ns at room temperature. this is the shortest on interval of the controlling fet. the controller either does not turn on the top mosfet at all or turns it on for at least 50ns. for a synchronous step-down converter, the operating duty cycle is vin vo / . so the required on time for the top mosfet is ( ) s f vin vo / . if the frequency is set such that the required pulse width is less than 50ns, then the converter will start skipping cycles. due to minimum on time limitation, simultaneously operating at applications information (continued) the non-inverting input of the frst feedback amplifer is tied to the internal 0.5v voltage reference. both the non- inverting and the inverting inputs of the second error amplifer are brought out as device pins so that the output of the second converter can be made to track the output of the frst channel. for example in ddr applications, channel can be used to generate vddq (2.5v) from the input (5v or 2v) and channel 2 is used to produce a tracking vtt ( .25v) with vddq being its input. current-limit the maximum current sense voltage of +75mv is the cycle-by-cycle peak current limit when the load is drawing current from the converter. there is no cycle-by- cycle current limiting when the inductor current fows in the negative direction. however once the valley of the current sense voltage exceeds - 0mv, the corresponding channel will undergo shutdown and restart (hiccup). soft-start and overload protection the undervoltage lockout circuit discharges the ss/en capacitors. after vcc rises above 4.5v, the ss/en capacitors are slowly charged by internal 2 m a current source. with internal pnp transistors, the ss/en voltages clamp the error amplifer outputs. when the error amplifer output rises to 2.2v, the high-side mosfet starts to switch. as the ss/ en capacitor continues to be charged, the comp voltage follows. the converter gradually delivers increasing power to the output. the inductor current follows the comp voltage envelope until the output goes into regulation. the ss/en clamp on comp is then released. after the ss/en capacitor is charged above 3.2v (high enough for the error amplifer to provide full load current), the overload detection circuit is activated. if the output voltage falls below 70% of its set value or the valley current-sense voltage exceeds - 0mv, an overload latch will be set and both the top and the bottom mosfets will be turned of. the ss/en capacitor is slowly discharged with an internal .4 m a current sink. the overload latch is reset when the ss/en capacitor is discharged below 0.5v. the ss/en capacitor is then recharged with the 2ua current source and the converter undergoes soft-start. if overload persists, the sc2443 will undergo repetitive shutdown and restart. if the output is short-circuited, the inductor current will not increase indefnitely between the time the inductor
sc2443 3 applications information (continued) very high switching frequency and very short duty cycle is not practical. if the voltage conversion ratio vin vo / and hence the required duty cycle is higher, the switching frequency can be increased to reduce the sizes of passive components. there will not be enough modulation headroom if the on time is simply made equal to the minimum on time of the sc2443. for ease of control, we recommend the required pulse width to be at least .5 times the minimum on time. setting the switching frequency the switching frequency is set with an external resistor connected from pin 24 to ground. the set frequency is inversely proportional to the resistor value (figure 2). figure 2. free running frequency vs. rosc. 0 100 200 300 400 500 600 700 800 0 50 100 150 200 250 rosc (k ohm) fs (khz) setting the output voltage the non-inverting input of the channel-one error amplifer is internally tied the 0.5v voltage reference output (pin 5). the non-inverting input of the channel-two error amplifer is brought out as a device pin (pin 6) to which the user can connect pin 5 or an external voltage reference. a simple voltage divider (ro at top and ro2 at bottom) sets the converter output voltage. the voltage feedback gain h=0.5/vo is related to the divider resistors value as pc board layout issues circuit board layout is very important for the proper operation of high frequency switching power converters. a power ground plane is required to reduce ground bounces. the following are suggested for proper layout: power stage ) separate the power ground from the signal ground. in the sc2443, the power ground pgnd should be tied to the source terminal of lower mosfets. the signal ground agnd should be tied to the negative terminal of the output capacitor. 2) minimize the size of high pulse current loop. keep the top mosfet, bottom mosfet and the input capacitors within a small area with short and wide traces. in addition to the aluminum energy storage capacitors, add multi- layer ceramic (mlc) capacitors from the input to the power ground to improve high frequency bypass. 3) reduce high frequency voltage ringing. widen and shorten the drain and source traces of the mosfet to reduce stray inductances. add a small rc snubber if necessary to reduce the high frequency ringing at the phase node. sometimes slowing down the gate drive signal also helps in reducing the high frequency ringing at the phase node. 4) shorten the gate driver path. integrity of the gate drive (voltage level, leading and falling edges) is important for circuit operation and efciency. short and wide gate drive traces reduce trace inductances. bond wire inductance is about 2~3nh. if the length of the pcb trace from the gate driver to the mosfet gate is inch, the trace inductance will be about 25nh. if the gate drive current is 2a with 0ns rise and falling times, the voltage drops across the bond wire and the pcb trace will be 0.6v and 5v respectively. this may slow down the switching transient of the mosfet. these inductances may also ring with the gate capacitance. 5) put the decoupling capacitor for the gate drive power supplies (bst and pvcc) close to the ic and power ground. control section 6) the frequency-setting resistor rosc should be placed close to pin 3. trace length from this resistor to the analog . 1 o 2 o r h 1 h r - =
sc2443 4 applications information (continued) ground should be minimized. 7) solder the bias decoupling capacitor right across the avcc and analog ground agnd. 8) place the inductor dcr sense components away from the power circuit and close to the corresponding cs+ and cs- pins. use x7r type ceramic capacitor for the dcr sense capacitor because of their temperature stability. 9) use an isolated local ground plane underneath the controller and tie it to the negative side of output capacitor bank. 0) comp pin is sensitive to noise. place compensation network components away from noise signal (i.e. gate driver signals, phase node) and close to corresponding comp pin .
sc2443 5 evaluation application circuit _ single output, current share confguration 12vin r20 1k c17 1500uf/6.3v/fl r2 10k c24 2.2nf c3 270uf/16v/oscon q6 ipd06n03la l1 1.5uh/1.8mr cs1- c14 10uf/6.3v c16 1500uf/6.3v/fl r10 2r2 r4 n.p. r3 1r c4 1uf c11 270uf/16v/oscon c19 10uf/6.3v r11 0r 1vout/40a c13 n.p c12 330pf q1 ipd09n03la cs1- in1- r7 0r c1 10uf/16v c9 1uf 12vin c18 n.p. u1 sc2443 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 in1- comp1 sync agnd ref refin comp2 in2- cs2- cs2+ ss2/en2 avcc bst2 gdh2 gdl2 pgnd pvcc gdl1 gdh1 bst1 ss1/en1 cs1+ cs1- rosc cs1+ r21 10r d2 1n4148 c20 1uf r14 n.p. q3 ipd06n03la c8 2.2nf r18 0r c25 1uf r9 47k c7 22nf r6 10r c23 100nf r12 10k r13 1r c15 1500uf/6.3v/fl cs1+ c6 22pf r17 0r q2 ipd06n03la q4 ipd09n03la d1 1n4148 c22 22pf r19 560r in1- c10 10uf/16v c5 100nf q5 ipd06n03la r16 10r r1 0r c21 100nf r15 1.05k 12vin c2 270uf/16v/oscon r8 560r l2 1.5uh/1.8mr r5 124k
sc2443 6 item reference quantity description package part vendor c,c0 2 6v x5r ceramic capacitor 206 0uf murata 2 c2,c3,c 3 6v aluminum solid capacitor _sepc series 8 x 9mm 270uf sanyo 3 c4,c9,c20,c25 4 6v x5r ceramic capacitor 0603 uf murata 4 c5,c2,c23 3 6v x7r ceramic capacitor 0603 00nf panasonic 5 c6,c22 2 25v x7r ceramic capacitor 0603 22pf panasonic 6 c7 16v x7r ceramic capacitor 0603 22nf panasonic 7 c8,c24 2 25v x7r ceramic capacitor 0603 2.2nf panasonic 8 c2 25v x7r ceramic capacitor 0603 330pf panasonic 9 c4,c9 2 6.3v x7r ceramic capacitor 206 0uf murata 0 c5,c6,c7 3 6.3v aluminum capacitor _ fl series 8 x .5mm 000uf panasonic d,d2 2 small signal diode smd n448 any 2 l,l2 2 smd inductor 2.5 x 2.5 x 0mm .5uh/.8mr trio 3 q,q4 2 30v n channel mosfet d-pack ipd09n03la infneon 4 q2,q3,q5,q6 4 30v n channel mosfet d-pack ipd06n03la infneon 5 r,r7,r, r7,r8 5 5% smd resistor 0603 0r any 6 r2,r2 2 5% smd resistor 0603 0k any 7 r3,r3 2 5% smd resistor 0603 r any 8 r5 % smd resistor 0603 24k any 9 r6,r6.r2 3 % smd resistor 0603 0r any 20 r8,r9 2 % smd resistor 0603 560r any 2 r9 5% smd resistor 0603 47k any 22 r0 5% smd resistor 0603 2r2 any 23 r5 % smd resistor 0603 .05k any 24 r20 % smd resistor 0603 k any 25 u dual phase sync. step down controller mlpq-24 sc2443 semtech evaluation board bill of materials single output current share confguration
sc2443 7 evaluation application circuit_ dual independant outputs q3 n.p. q1 ipd09n03la r6 124k c17 n.p. r4 n.p. sync r17 4.12k r24 0r r12 2r2 cs1+ q4 ipd09n03la c24 22uf/10v/x7r c29 22nf c16 470pf cs1- q6 n.p. r9 n.p. c10 1800uf/6.3v/fl c15 1500uf/16v/fl l1 2.2uh/2mr 12vin 12vin q5 ipd06n03la c21 22uf/10v/x7r c9 1800uf/6.3v/fl cs1+ c6 27pf c25 2.2nf c28 n.p. c19 100nf r19 0r r2 15k r22 1k r16 n.p. c14 10uf/16v r21 n.p. c30 1uf c5 100nf r8 0r l2 2.2uh/2mr r15 1r c12 2.2nf r10 1k r5 1.05k c7 22nf c20 n.p. c22 2200uf/6.3v/fl cs1- c1 10uf/16v 1n1- r11 47k c4 1uf r13 0r d1 1n4148 12vin r14 20k c2 1500uf/16v/fl r1 0r c8 10uf/6.3v r7 0r c23 2200uf/6.3v/fl u1 sc2443 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 in1- comp1 sync agnd ref refin comp2 in2- cs2- cs2+ ss2/en2 avcc bst2 gdh2 gdl2 pgnd pvcc gdl1 gdh1 bst1 ss1/en1 cs1+ cs1- rosc r23 10r r3 1r r18 0r q2 ipd06n03la c26 100nf in1- c18 1uf c3 n.p. d2 1n4148 r20 100k r25 0r 2.5vout/20a c27 470pf c13 1uf 1vout/20a c11 10uf/6.3v
sc2443 8 item reference quantity description package part vendor c,c4 2 6v x5r ceramic capacitor 206 0uf murata 2 c2,c5 2 6v aluminum capacitor _fl series 0 x 20mm 500uf panasonic 3 c4,c3,c8, c30 4 6v x5r ceramic capacitor 0603 uf murata 4 c5,c9,c26 3 6v x7r ceramic capacitor 0603 00nf panasonic 5 c6 25v x7r ceramic capacitor 0603 27pf panasonic 6 c7,c29 2 16v x7r ceramic capacitor 0603 22nf panasonic 7 c8,c 2 6.3v x7r ceramic capacitor 206 0uf murata 8 c9,c0 2 6.3v aluminum capacitor _ fl series 0 x 6mm 800uf panasonic 9 c2,c25 2 25v x7r ceramic capacitor 0603 2.2nf panasonic 0 c6,c27 2 25v x7r ceramic capacitor 0603 470pf panasonic c2,c24 2 0v x7r ceramic capacitor 206 0uf murata 2 c22,c23 2 6.3v aluminum capacitor _ fl series 0 x 20mm 2200uf panasonic 3 d,d2 2 small signal diode smd n448 any 4 l,l2 2 through hole inductor 2.2uh/2mr any 5 q,q4 2 30v n channel mosfet d-pack ipd09n03la infneon 6 q2,q5 2 30v n channel mosfet d-pack ipd06n03la infneon 7 r,r7,r,r3, r8,r9,r24 r25 8 5% smd resistor 0603 0r any 8 r2 5% smd resistor 0603 5k any 9 r3,r5 2 5% smd resistor 0603 r any 20 r5 % smd resistor 0603 .05k any 2 r6 % smd resistor 0603 24k any 22 r0,r22 2 % smd resistor 0603 k any 23 r 5% smd resistor 0603 47k any 24 r2 5% smd resistor 0603 2r2 any 25 r4 5% smd resistor 0603 20k any 26 r7 % smd resistor 0603 4.2k any 27 r20 5% smd resistor 0603 00k any 28 r23 5% smd resistor 0603 0r any 29 u dual phase sync. step down controller mlpq-24 sc2443 semtech evaluation board bill of materials dual independent output confguration
sc2443 9 evaluation application circuit_ dual independant outputs (lower power application) 5 5 4 4 3 3 2 2 1 1 d d c c b b a a a sc2443 dual indepe ndant outputs 1 1 tuesday, december 11, 2007 title size document number rev date: sheet of vin 12vin 1.5vout 1.8vout 12vin c7 22nf c30 1uf c9 1000uf/6.3v/fl u1 sc2443 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 in1- comp1 sync agnd ref refin comp2 in2- cs2- cs2+ ss2/en2 avcc bst2 gdh2 gdl2 pgnd pvcc gdl1 gdh1 bst1 ss1/en1 cs1+ cs1- rosc c6 27pf q1 fds6982 r8 0r c11 n.p c17 n.p. r12 2r2 c27 470pf r6 102k r9 604r c5 100nf/x7r c23 n.p l2 1.9uh/3.9mr r11 47k r3 1r c24 n.p r1 0r d1 1n4148 c1 10uf/16v c18 1uf c13 1uf c26 100nf r25 0r c25 2.2nf c10 n.p r16 n.p. c29 22nf r4 n.p. c28 n.p. c14 10uf/16v r5 2.05k c16 470pf r24 0r d2 1n4148 r22 1k l1 1.9uh/3.9mr r19 0r r14 4.87k q2 fds6982 r10 1k c21 10uf/6.3v/x7r c19 100nf/x7r r21 604r c12 2.2nf r15 1r r20 47k c8 10uf/6.3v c22 1000uf/6.3v/fl r13 0r c4 1uf c2 680uf/16v/fl r18 10r r17 2.61k r7 10r c20 18pf r2 4.87k r23 10r c15 680uf/16v/fl cs1+ cs1- cs1+ cs1- 1n1- in1- sync
sc2443 20 item reference quantity description package part vendor c,c4 2 6v x5r ceramic capacitor 206 0uf murata 2 c2,c5 2 6v aluminum capacitor _fl series 0 x 2.5mm 680uf panasonic 3 c4,c3,c8, c30 4 6v x5r ceramic capacitor 0603 uf murata 4 c5,c9,c26 3 6v x7r ceramic capacitor 0603 00nf panasonic 5 c6 25v x7r ceramic capacitor 0603 27pf panasonic 6 c7,c29 2 16v x7r ceramic capacitor 0603 22nf panasonic 7 c8,c2 2 6.3v x7r ceramic capacitor 206 0uf murata 8 c9,c22 2 6.3v aluminum capacitor _ fl series 0 x 2.5mm 000uf panasonic 9 c2,c25 2 25v x7r ceramic capacitor 0603 2.2nf panasonic 0 c6,c27 2 25v x7r ceramic capacitor 0603 470pf panasonic c20 25v x7r ceramic capacitor 0603 8pf murata 2 d,d2 2 small signal diode smd n448 any 3 l,l2 2 through hole inductor .9uh/3.9mr any 4 q,q2 2 30v n channel mosfet so-8 fds6982 fairchild 5 r,r8,r3, r9,r24,r25 6 5% smd resistor 0603 0r any 6 r2,r4 2 5% smd resistor 0603 4.87k any 7 r3,r5 2 5% smd resistor 0603 r any 8 r5 % smd resistor 0603 2.05k any 9 r6 % smd resistor 0603 02k any 20 r7,r8,r23 3 5% smd resistor 0603 0r any 2 r9,r2 2 5% smd resistor 0603 604r any 22 r0,r22 2 % smd resistor 0603 k any 23 r,r20 2 5% smd resistor 0603 47k any 24 r2 5% smd resistor 0603 2r2 any 25 r7 % smd resistor 0603 2.6k any 26 u dual phase sync. step down controller mlpq-24 sc2443 semtech evaluation board bill of materials dual independent output confguration
sc2443 2 outline drawing - mlpq-24 ? semtech, inc. all rights reserved. an iso-registered company. semtech cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a semtech product. no circuit patent licenses are implied. semtech reserves the right to change the circuitry and specifcations without notice at any time. trademarks and copyrights belong to their respective holders. ? 2007 semtech corporation e1 e bxn d/2 lxn inches .020 bsc b .007 bbb aaa n d1 e l e d .012 .100 dim a1 a2 a min .000 - .031 0.30 0.18 .012 0.25 .010 0.50 2.80 0.30 2.55 .004 .004 24 .016 .157 .106 .020 .110 0.10 0.10 24 0.40 4.00 2.70 0.50 bsc millimeters max 0.05 - 1.00 dimensions min 0.00 - nom (.008) .035 .001 max .002 - .039 nom 0.80 0.02 (0.20) 0.90 controlling dimensions are in millimeters (angles in degrees). coplanarity applies to the exposed pad as well as the terminals. notes: 2. 1. 1 2 n e1 .100 .106 .110 2.55 2.70 2.80 pin 1 indicator 4.15 3.85 4.00 4.15 3.85 .157 .152 .163 .152 .163 aaa c a c (laser mark) d e b a1 a a2 seating plane e/2 bbb c a b d1
sc2443 22 land pattern - mlpq-24 company's manufacturing guidelines are met. 4.80 .189 z k g z h (c) x p functional performance of the device. shall be connected to a system ground plane. thermal vias in the land pattern of the exposed pad failure to do so may compromise the thermal and/or 2. this land pattern is for reference purposes only. consult your manufacturing group to ensure your notes: 1. dim x y h k p c g millimeters inches (3.95) .010 .033 .122 .020 .106 .106 (.156) 0.25 0.85 2.70 0.50 2.70 3.10 dimensions semtech corporation power management products division 200 flynn road, camarillo, ca 930 2 phone: (805) 498-2 fax: (805) 498-3804 www.semtech.co m contact information

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